On top of a ferroelectric memory, a pad is provided to which a wiring or the like is connected from the outside. FIG. 6 is a cross-sectional view showing a structure of a conventional ferroelectric memory.
In the conventional ferroelectric memory, a transistor (not shown) is formed on a silicon substrate (not shown), and an interlayer insulation film 52 is formed above them. On the interlayer insulation film 52, a ferroelectric capacitor 51 is formed which includes a bottom electrode 51a, a ferroelectric film 51b, and a top electrode 51c. An interlayer insulation film 53 covering the ferroelectric capacitor 51 is formed on the interlayer insulation film 52. A hole reaching the transistor and the like is formed in the interlayer insulation films 52 and 53, and a plug 54 is formed in the hole. Further, holes reaching the top electrode 51a and the bottom electrode 51c are also formed in the interlayer insulation film 53, and wirings 55 are formed in the holes and on the plug 54. An alumina film 56 covering the wirings 55 is formed, and an interlayer insulation film 57 is formed on the alumina film 56. A hole reaching the wiring 55 is formed in the alumina film 56 and the interlayer insulation film 57, and a plug 58 is formed in the hole. On the interlayer insulation film 57, wirings 59 are formed. An interlayer insulation film 60 covering the wirings 59 is formed on the interlayer insulation film 57. Holes reaching the wirings 59 are formed in the interlayer insulation film 60, and plugs 64 are formed in the holes.
On the interlayer insulation film 60, wirings 65 are formed which also serve as pads. A silicon oxide film 66 and a silicon nitride film 67 are formed which cover the wirings 65. The thicknesses of the silicon oxide film 66 and the silicon nitride film 67 are about 100 nm and about 350 nm, respectively. A pad opening 68 exposing a portion of the wiring 65 is formed in the silicon oxide film 66 and the silicon nitride film 67. On the silicon nitride film 67, a polyimide film 70 is formed. The silicon oxide film 66 is formed using TEOS (tetraethylorthosilicate) or the like.
The silicon nitride film 67 having a larger thickness can suppress entry of hydrogen and moisture from the outside more. However, a gas containing H (hydrogen) is used at the time of forming the silicon nitride film 67, and therefore if the silicon nitride film 67 is formed thick, hydrogen adversely affecting the ferroelectric film 51b will enter the inside at the time of formation thereof. In consideration of these circumstances, the thickness of the silicon nitride film 67 is set to about 350 nm in the conventional ferroelectric memory.
However, in the combination of the silicon oxide film 66 of about 100 nm and the silicon nitride film 67 of about 350 nm, cracks may occur in the silicon nitride film 67 during use or the like to allow hydrogen, moisture and the like to enter the inside. If such entry occurs, PTHS (Pressure Temperature Humidity Stress) defects and/or single-bit defects may be induced. The causes of such cracks include a low flatness of the silicon nitride film 67. Making the silicon oxide film 66 thick can improve the flatness of the silicon nitride film 67. However, if a thick silicon oxide film 66 is formed using TEOS, a large amount of moisture in the silicon oxide film 66 can diffuse down to the ferroelectric capacitor during the subsequent heating process and the like.
For such situation, a thick SOG (Spin On Glass) film may be used as a silicon oxide film constituting the covering film in a semiconductor device having no ferroelectric capacitor such as a DRAM (Dynamic random Access Memory) or the like.
However, the SOG film cannot be applied to the ferroelectric memory. This is because it is necessary to perform thermal processing at a high temperature in order to form the SOG film, and a large amount of hydrogen and moisture diffuses during the thermal processing. In addition, the SOG film itself has a high hygroscopicity so that the moisture absorbed by the SOG film after formation can diffuse down to the ferroelectric capacitor afterward.
Patent Document 1
Japanese Patent Application Laid-open No. 2001-36026
Patent Document 2
Japanese Patent Application Laid-open No. 2001-15703